1. Field of the Invention
The present invention relates to a trench-type vertical semiconductor device such as a trench-type vertical metal oxide semiconductor (MOS) transistor and a trench-type vertical insulated gate bipolar transistor (IGBT).
Generally, since trench-type vertical MOS transistors and IGBTs are easy to control and have negative temperature coefficient ON-currents, they have been used as power semiconductor devices for driving inductance loads such as motors and solenoid values in automobiles. When such inductance loads are driven by the above-mentioned MOS transistors or IGBTs, it is important that an avalanche breakdown phenomenon caused by the inductance loads should be suppressed.
2. Description of the Related Art
A first prior art trench-type vertical semiconductor device is constructed by gate electrodes buried in trenches each of which has a uniform width. In this case, the bottom of a base region reaches an intermediate portion of each of the trenches. This will be explained later in detail.
In the above-described first prior art semiconductor device, however, a breakdown current flows due to the counter-electromotive force of an inductance load to turn ON a parasitic bipolar transistor. As a result, the breakdown current is concentrated on the base region, which would destroy the semiconductor device.
In a second prior art semiconductor device (see: JP-2000-058823-A), impurity diffusion regions are added to the first prior art semiconductor device, so that the turning-ON of the parasitic bipolar transistor is suppressed, so that the destruction of the semiconductor device can be suppressed. This also will be explained later in detail.
In the above-described second prior art semiconductor device, however, when the added impurity diffusion regions are close to the gate electrodes, i.e., the channel regions of a MOS transistor, the cut-off voltage and ON-resistance of the MOS transistor would be increased. Also, the breakdown voltage characteristics would deteriorate. Thus, it is difficult to control the depth and impurity concentration of the added impurity diffusion regions.
In a third prior art semiconductor device (see: JP-2001-244325-A), rounded hump openings are provided at the bottoms of trenches thus relaxing the current concentration, which would suppress the reduction of a gate breakdown voltage.